Safety and security of HW primitives (Cipher blocks, PUF, JTAG…)

WP3 will deal with the safety and security of hardware primitives operating in harsh and critical environments and against physical attacks (hardware security). All the partners are involved in this work package. Innovation concerning hardware safety and security will stem from including new technologies, applications, mitigation techniques, attacks, and countermeasures in the curriculum of the involved European universities. The cooperation between the partners of the project will effectively achieve the transferability of knowledge and know-how among the master programs of the partner Universities, the professors, and the students.

WP3 is composed of three sub-work packages ( WP3.1, WP3.2, WP3.3 ):

• WP3.1 focuses on the creation of new lectures and labs on basic principles of hardware security as well as attacks and countermeasures for FPGAs.
  • WP3.1.1: Hardware security introductory lecture (source UPC, source Univ. of Freiburg)
  • WP3.1.2: Hardware security attacks and countermeasures for FPGAs (Side-channel Analysis on FPGAs lab + source)
• WP3.2 aims to integrate into curriculums, state-of-the-art security primitives.
  • WP3.2.1: Educational content for PUF and PUF-based computation (lecture)
• WP3.3 targets the reliability and fault tolerance of security primitives and FPGAs.
  • WP3.3.1: Functional verification of secure circuits (lecture)

The present sub-page will be updated soon with the obtained results of WP3.